Floating-gate Mos Synapse Transistors
نویسندگان
چکیده
منابع مشابه
A Floating-Gate MOS Learning Array with Locally Computed Weight Updates
We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-...
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